The assignment will be graded out of 100 points. Create a text document entitled answers.xxx (where you replace xxx with whatever extension is appropriate, depending on the file format you use). Acceptable file formats are plain text, Word document, OpenOffice document, and PDF. Put your name and UTA ID on the first line of the document. Submit this document to Blackboard before the deadline. You will be able to revise your answers until the deadline with no penalty.
add A B C
: Adds contents of registers B and C, stores result in register A.
addi A C N
: Adds integer N to contents of register C, stores result in register A.
load A address
: Loads data from the specified memory address to register A.
store A address
: Stores data from register A to the specified memory address.
goto line
: The next instruction should be the specified line.
if A line
: If the contents of register A are NOT 0, the next instruction should be the specified line.
load R1 address1
addi R3 R1 20
load R2 address2
if R2 6
add R2 R1 R2
addi R5 R2 50
addi R6 R1 20
addi R7 R1 30
store R7 address10
store R6 address11
store R5 address12
address1
contains
integer 10, and address2
contains integer 5. Show how the instructions are executed through the pipeline step-by-step, until the program finishes running. Use a table where each row is a time step, each column is one of the 5 pipeline steps (instruction fetch, decode, operand fetch, execute operation, write back result), and at each entry in the table you show which line of code is at that specific step at that specific time (similar to how it was done in the slides, but switching rows with columns). Mark with an 'X' entries in the table where no instruction is executed.
In computing your answer, you should not consider the entire table. You should start from (and including) the time that the first instruction arrives at the last step of the pipeline, and you should stop at (and including) the time that the last instruction arrives at the first step of the pipeline.
Part b (5 pts): Discuss why you should not consider the entire table when measuring the pipeline utilization percentage.
address10, address 11, address12
at the end of execution) will always be identical to what it would be without reordering the instructions, for any possible initial contents of address1, address2
.
address2
contains integer 5.
Consider the operation of a machine with the data path of Fig. 2-2. Suppose that loading the ALU input registers takes 5 nsec, running the ALU takes 10 nsec, and storing the result back to a register takes 5 nsec. What is the maximum number of MIPS this machine is capable of in the absence of pipelining?
On computer 1, all instructions take 10 nsec to execute. On computer 2, they all take 5 nsec to execute. Can you say for certain that computer 2 is faster? Discuss.
Imagine you are designing a single-chip computer for an embedded system. The chip is going to have all its memory on chip and running at the same speed as the CPU with no access penalty. Examine each of the principles discussed in Sec. 2.1.4 and tell whether they are so important (assuming that high performance is still desired).
Sociologists can get three possible answers to a typical survey question such as "Do you believe in the tooth fairy?" - namely, yes, no, and no opinion. With this in mind, the Sociomagnetic Computer Company has decided to build a computer to process survey data. This computer has a trinary memory. That is, each byte (tryte?) consists of 8 trits, with a trit holding a 0, 1, or 2. How many trits are needed to hold a 6-bit number? Give an expression for the number of trits needed to hold n bits of data.
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